A device combining a metal-oxide-semiconductor (MOS) transistor and a bipolar transistor is advantaged in that the configuration of a drive circuit is simple, as in a MOS element, and ON resistance is low due to the conductivity modulation of a withstand voltage part, as in a bipolar transistor. As a result of these advantages, such devices are gaining importance in fields requiring a high withstand voltage and a large power level. This type of device has a planar gate structure or a trench gate structure. In the planar gate structure, a gate electrode is provided on a substrate surface via a gate insulating film. In the trench gate structure, the gate electrode is buried in a trench formed in the substrate. A device having a trench gate structure is advantaged in that high channel density can be achieved, parasitic thyristors do not operate easily, and so on.
A conventional insulated-gate-bipolar transistor (IGBT) configuration will be described below with reference to the drawings. Note that in the specification and the drawings, the symbols n and p added to the names of semiconductor layers and regions indicate that the majority carrier of the corresponding layer or region is an electron and a hole, respectively. Further, when + is affixed to n or p, as in n+ and p+, this shows that the impurity concentration of the corresponding semiconductor layer or region is higher than the impurity concentration of a semiconductor layer or region to which + is not affixed. Further, when − is affixed to n or p, as in n− and p−, this shows that the impurity concentration of the corresponding semiconductor layer or region is lower than the impurity concentration of a semiconductor layer or region to which − is not affixed.
FIG. 49 is a view showing the sectional configuration of an IGBT manufactured using a conventional thick-film silicon-on-insulator (SOI) substrate. Here, the SOI substrate is configured such that an n− drift region 103 having high resistivity and serving as an active layer is laminated onto a support substrate 101 via an insulating layer 102. A p base region 104 is provided on a part of a surface layer of the n− drift region 103. An n+ emitter region 106 and a p+ low resistance region 105 that contacts the n+ emitter region 106 are provided on a part of the surface layer of the p base region 104. A part of the p+ low resistance region 105 occupies a part below the n+ emitter region 106. Further, an n buffer region 111 is provided on a part of the surface layer of the n− drift region 103 spaced from the p base region 104. The resistivity of the n buffer region 111 is lower than the resistivity of the n− drift region 103. A p+ collector region 112 is provided on a part of the surface layer of the n buffer region 111. An emitter electrode 107 contacts both the p+ low resistance region 105 and the n+ emitter region 106. A gate electrode 108 is provided on the surface of the p base region 104, which is sandwiched between the n− drift region 103 and the n+ emitter region 106, via an insulating film 109. A collector electrode 110 contacts the p+ collector region 112.
In the IGBT configured in FIG. 49, a PNP bipolar transistor is constituted by the p+ collector region 112, an n region constituted by the n buffer region 111 and the n− drift region 103, and a p region constituted by the p base region 104 and the p+ low resistance region 105. Further, an NPN bipolar transistor is constituted by the n+ emitter region 106, the p base region 104, and the n− drift region 103. The PNP bipolar transistor and NPN bipolar transistor together form a parasitic thyristor. To avoid latchup caused by the parasitic thyristor, an upper limit is set in relation to an ON current. To increase the upper limit value of the ON current, measures can be taken to ensure that the NPN bipolar transistor is not activated. For this purpose, the resistance of a current path passing below the n+ emitter region 106 from a channel end side to the p+ low resistance region 105 must be suppressed. A method of reducing the resistance of the current path through ion implantation is well known. Further, in a well-known method of forming a trench emitter electrode that is capable of self-alignment with a gate electrode, uncertainty when forming the p+ low resistance region 105 is removed through mask alignment, and the length of the current path is reduced to a minimum.
A structure in which part of the carrier that flows into the n− drift region 103 from the p+ collector region 112 is caused to arrive at the p+ low resistance region 105 without passing through the current path when the element is in an ON state is also well known. In the IGBT shown in FIG. 49, an electric field is concentrated on the interface between the n− drift region 103 and the p base region 104 in the vicinity of the wafer surface, and the interface between the n− drift region 103 and the n buffer region 111 in the vicinity of the wafer surface. To reduce this electric field concentration, the emitter electrode 107 and collector electrode 110 can be extended to cover these interfaces via the insulating film 109 as field plates. In a well-known structure employed when a higher withstand voltage is required or wiring such as a power line exists on the drift region, a capacitively coupled field plate is provided on the upper surface of the drift region on the wafer surface or in the interior of the drift region.
In a conventional device combining a MOS transistor and a bipolar transistor, such as that described above, a voltage is supported in the direction of the wafer surface, and therefore the dimensions of a unit device increase in proportion with the withstand voltage design value. Therefore, a device used for high-withstand voltage, large-current applications is disadvantaged in that the chip area increases. To reduce the surface area of the drift region on the wafer surface in a lateral MOS transistor, a configuration in which a trench is formed in the drift region and the trench is filled with a silicon oxide film having a greater breakdown electric field than silicon has been proposed for example in Japanese Unexamined Patent Application Publication H8-97411. According to this proposal, as shown in FIG. 50, an effective drift length Leff corresponds to a length obtained by adding together a distance LP from an interface between a p well region 204 formed with a channel and an n well region 203 that serves as the drift region to an oxide film 217 buried in the trench, a trench depth LT, a trench width LB, and the trench depth LT again. Meanwhile, a distance LD from the interface between the p well region 204 and n well region 203 on the wafer surface to a drain region 212 corresponds to a length obtained by adding together LP and LB. Accordingly, Leff can be made longer than when the buried oxide film 217 is not provided, and therefore an ON resistance RonA is reduced in comparison with a device having an identical withstand voltage. Here, Ron is the ON resistance per unit area, and A is the surface area. In other words, a lateral device having an equal withstand voltage and an equal ON current to a conventional device and a smaller device pitch than a conventional device is obtained.
Further, in a lateral IGBT having an SOI (silicon on insulator) structure, a configuration in which a trench is formed in an n-type active layer and a high-density n-type bypass layer is provided partially below the trench has been proposed for example in Japanese Unexamined Patent Application Publication H8-88357 (FIGS. 1 to 8) (hereafter the second reference). According to this proposal, a hole current that flows into a source electrode is reduced by the trench, and an electron current flows through the bypass layer. Therefore, electron current accumulation on the source side increases, leading to a reduction in the ON voltage.
However, various problems exist in the IGBT disclosed in the second reference. For example, when a wafer is realized by adhering a SOI structure, two wafers must be adhered with positioning precision in the order of μm to ensure that the bypass layer is positioned directly beneath the trench, and this is unfavorable in terms of manufacture. Further, with the layout shown in FIG. 2 or 3 of the second reference, the withstand voltage is determined according to the length of the n-type active layer on the wafer surface, and therefore the cell pitch of the device cannot be shortened. As a result, the ON resistance per unit area cannot be reduced. Further, when the sectional configuration shown in FIG. 8 of the second reference is provided with the layout shown in FIG. 4 thereof, a low resistance region exists on the periphery of the trench, and therefore the withstand voltage is determined according to the length of the n-type active layer on the wafer surface excluding the trench. Hence, the cell pitch of the device cannot be shortened, and as a result, the ON resistance per unit area cannot be reduced. Further, with a device having the layout shown in FIG. 4 and the sectional configuration shown in FIG. 6 of the second reference, a hole passage is not formed beneath the trench 17, and therefore conductivity modulation on the gate side is not performed such that the benefits of the IGBT are impaired. If the layout shown in FIG. 2 of this publication is employed to maintain gate side conductivity modulation, the device pitch is determined according to the length of a surface drift region 3, and therefore the pitch cannot be shortened. Furthermore, with the sectional configuration shown in FIG. 5 of the second reference, the distance of the active layer between the trench bottom and the bypass layer is determined in accordance with ion implantation energy, and therefore this part cannot be increased in thickness, thereby limiting tradeoff with the withstand voltage.
Accordingly, there remains a need for lateral IGBT that enables driving at a high withstand voltage and a large current, and has high latchup immunity and low ON resistance per unit area. The present invention addresses this need.